Yet another Radio Clock
One more radio clock
For no particular reason except my own entertainment, I've started to build yet
another radio clock. I don't keep up with counting them, so I don't know how many
of them I've built before.
A few that I remember of:A kit named "DOC 85" - basically just assembled it
An early homemade radio clock based on a TCA whatever AM receiver chip and an 8051 MCU for decoding and display control. Coding was done in pure 8051 assembler.
Used an IR transmitter to push the demodulated DCF77 pulses into the IRDA port of a laptop, running ntpd to decode it.
Wrote and embedded an DCF decoder into a measurement instrument, using an external ready made DCF77 receiver module. The MCU used for decoding
was a NEC V25 (8086 compatible), coded in Turbo Pascal
Wrote and embedded another DCF / high precision PPS decoder into another measurement instrument, this time using an ADSP-2181 DSP. Coding was ADSP-2181 assembler and/or
Ported the above decoder to yet another instrument, using a Hitachi SH2 processor. Coded in pure embedded C
An attempt to make a noise / disturbance tolerant radio clock using an Infineon XE167 MCU.
Implemented a dual channel DCF / PPS receiver to an STM32F7 nucleo board. This one provides time and date to my home CAN network.
Note, these are all DC77 (German / European time standard) radio clocks. Most of the above is lost or not available for public disclosure.
Another common "feature" of these radio clocks is: All of them use the DCF77 AM (amplitude modulation) time code only. This is pretty common
for most commercially available radio clocks.
So let's go for something completely different
The DCF77 doesn't transmit the time code amplitude modulated (AM) alone, but also on PM (phase modulation). See the
DCF77 Wikipedia article for a detailed description. The PM receiving method
provides one with superiour time accuracy in comparison with the usual AM receivers, though it's not as accurate as an GPS timing receiver.
So the goal for is set: Build a Phase Modulation DCF77 radio clock with some robustness in time code decoding. Additionally, this radio
clock will provide a 10MHz reference frequency and a PPS (pulse per second) output.
What's the purpose of that ferrite rod sitting in the junk box? As so often with this kind of stuff, it
just happens to be there. Now can I do something useful with it?
Yes, I can. Make an DCF77 antenna. Use isolated wire and apply an arbitrary amount of turns to the
rod - the more the better. Now add some capacitance to create a resonant tank and tune the whole
thing to the DCF77 carrier frequency (77.5kHz). Add a few turns in a separate winding to tap the received signal:
Using an oscilloscope with a highly sensitive input, one can see now the received DCF77 carrier.
By rotating the antenna rod, one can evaluate the directivity of this construction. If one uses
such kind of antenna to take a bearing of the transmitter, one rotates the antenna to minimum
signal level. The transmitter is now aligned to the longitudinal direction of the antenna.
Some gain required
As one can see, the output level is rather low. An amplifier is required. Nothing spectacular in this case,
just a chain of three OP-Amps, each one having a gain of 15 (23dB), resulting in a total gain of 3375 (70dB).
Depending on the size of the antenna / reception conditions / distance to the transmitter, this might require
some adjustment later on. There's a last stage in the amplifier, creating a 180° phase shifted (inverted)
signal to feed the mixer with a differential signal:
Mix it down to DC
Now feed a synchronous rectifier with that signal. In fact, use two synchronous rectifiers, one in-phase
and one quadrature. As these mixers are implemented using analog switches that are reversing the polarity
of the signal, I'd rather call them rectifiers than mixers. Although your typical diode ring mixer works
the same way and is called a mixer.
The mixer requires two LO signals: Both of them at the 77.5kHz carrier frequency, but having a 90°
phase shift. I'm using a CPLD to create these signals from the 10MHz master clock.
Low pass filter
The rectifiers output must be converted to a single ended signal and one wants to apply a bit
of low pass filtering. A final OP-Amp stage takes care of this:
That's all she wrote. At least for the analog signal processing part.
See the complete analog schematic page here.
The receiver requires an accurate 77.5kHz I/Q clock frequency to demodulate the signal.
A commonly used reference frequency for all kind of purposes is 10MHz. So I decided to
create all the required frequencies from a single 10MHz source. Your favourite calculator
tells there's no even divider ratio (not even an odd one) from 10MHz to 77.5kHz. To create
even more difficulties, usually one uses four times the carrier frequency (say 310kHz) as
an input to a divide-by-four circuit to create the in-phase and quadrature clocks. 10M divided
by 310k results in 32.25806452. By chance, this equals 1000/31 or 32 8/31.
10MHz by 32 results in 312.5kHz. 310kHz / 312.5kHz gives an (124/125)/32 ratio (which suprisingly
equals 1000/31) required to get 310kHz from 10MHz. So one can use
an divide-by-32 circuit and skip some pulses (one out of 125) to make up that division ratio. It's all
implemented in a few lines of VHDL code and runs within a small CPLD.
See the clock generator schematic page here.
Digital Signal Processing
No, not a fancy Digital Signal Processor here, but a Cortex-M4 based MCU. For lazyness,
I've used a STM Nucleo-32 Module. Due to the memory (especially large RAM buffers) requirements of the
demodulator and decoder, this turned out to an STM32L432 based module.
See the MCU schematic page here.
And the whole shebang: DCF77 radio clock prototype schematic.
The above resulted in this prototype, built using some modules on a perfboard:
Here's the latest source code archive (including the CPLD sources) for this prototype: Prototype source tarball
Gain some track
To get an idea of how the whole thing is intended to work, I've created a block diagram:
Click the image for a higher resolution version (works for the other images too).
Another block diagram, showing the details of the CPLD clock generation logic:
While drawing the latter diagram, I noticed the divider chain for generating a slighly offset carrier frequency
beeing unnecessarily complex. A simple 125/126 clock pulse skip would have done the job, not that
cascaded 125/126 and 124/125 logic that I struggle to understand now by myself. That's one of the downsides
of the modern stuff, one can easily pin down some VHDL code that works and fulfils the job, but is too
complex from a hardware view.
Anyway, it works, and its purpose is as said to generate a slightly offset 77.5kHz LO frequency. This
is required for the ADC auto offset calibration routine. The demodulator outputs a small DC offset
that must be subtracted from the signal to make the phase detection work at low signal levels.
As the demodulator is intended to mix down the signal to DC, there's no easy way to discriminate
the signal from the offset. Slightly changing the LO frequency does the trick then. By doing so,
the demodulators output a low frequency AC signal that gets averaged over some periods. By
averaging, the offset (still the DC part of the signal) is measured seperately from the signal
(now the LF AC signal) and is used to compensate for the offset error while the LO is running
at its nominal frequency. Some means to not mess up the LO phase isn't shown in the
block diagram. The automatic offset compensation is run about every three minutes.
Debugging and testing the DCF77 time code decoder firmware required a means to generate arbitrary time codes.
Especially the code transitions at DST / regular time switchover and leap second insertion were kind of
interesting. Say - it took a significant amount of effort to get these work seamlessly.
To simulate arbitrary time codes, I've put together a simple DCF77 transmitter. Its output signal
is directly coupled to the ferrite rod antenna by applying a third winding to it:
I've used just another STM32 nucleo board to make up the simulator. As the on-board
8MHz crystal isn't adjusted at all, it's deviation is too large for the receiver PLL
to lock. So I've used the 10MHz output from the receiver to clock the simulator.
Two of the Timers are used to create 90° phase shifted PWM signals representing
the I and Q of the AM/PM modulated carrier. A simple resonant tank takes care of
filtering the ugly PWM to a (more or less) nice sine wave. That signal is tapped from
the transformer, attenuated and coupled into the receiver:
The time code encoder uses the very same C code as the reference time code encoder
of the receiver, so once the simulator is verified to produce the correct codes,
the receiver is believed to use the correct time code to correlate against the
I've added some gizmos to the orignal schematic and created a layout. Ordered some PCBs:
KiCAD project is provided here for your convenience.
Created from that, the schematic as a PDF.
More to go
Waiting for the PCBs to be produced and delivered ...
References and Credits
While building the clock, of course I did some research on the Internet and found
a bit of documentation of how an DCF77 PM receiver should work, what accuracy
one can expect and some ideas on how to make a robust time code decoder:
Some interesting documents found on the almigthy Internet
Another DCF77 decoder library
A paper about a robust DCF77 AM/PM receiver
A paper by the PTB regarding the PM receiver
These inspired me to create this receiver. Although my design isn't a copy of any of these,
you'll find part of their concepts and ideas in my design.
So a big "Thanks" to the authors of this stuff.